1. Field of the Invention
The invention relates to an epitaxially coated silicon wafer and a method for producing epitaxially coated silicon wafers.
2. Background Art
Epitaxially coated silicon wafers are suitable for use in the semiconductor industry, in particular for the fabrication of large scale integrated electronic components such as microprocessors or memory chips. Starting materials (substrates) with stringent requirements are required for modern microelectronics, for example global and local flatness, edge geometry, thickness distribution, single-side-reference local flatness (nanotopology) and freedom from defects.
According to the prior art, a silicon wafer can be produced by a process sequence of separating a single crystal of silicon into wafers, rounding the mechanically sensitive edges, carrying out an abrasive step such as grinding or lapping followed by a polishing. EP 547894 A1 describes a lapping method; grinding methods are claimed in the applications EP 272531 A1 and EP 580162 A1.
The final flatness is generally produced by a finish polishing, which may be preceded, if appropriate, by an etching step for removing disturbed crystal layers and for removing impurities. A suitable etching method is known from DE 19833257 C1, by way of example. While traditional single-side polishing methods generally lead to poorer plane-parallelisms, polishing methods acting on both sides (“double-side polishing”) make it possible to produce silicon wafers with improved flatness. In the case of polished silicon wafers, the desire is to achieve the required flatness by suitable processing steps such as grinding, lapping and polishing.
On the other hand, DE 19938340 C1 describes providing a monocrystalline silicon wafer with a layer grown in monocrystalline fashion and made of silicon with the same crystal orientation, a so-called epitaxial coating, on which electronic components are later applied. Epitaxially coated silicon wafers have certain advantages over silicon wafers made of homogeneous material, for example in preventing charge reversal in bipolar CMOS circuits followed by short circuiting of the component (“latch-up”); lower defect densities, for example reduced number of COPs (“crystal-originated particles”); and also the absence of appreciable oxygen content, which precludes the risk of short-circuiting due to oxygen precipitates in component-relevant regions.
According to the prior art, epitaxially coated silicon wafers are produced from suitable preliminary products by means of a process sequence of removal polishing-final polishing-cleaning-epitaxy. DE 10025871 A1, for example, discloses a method for producing a silicon wafer with an epitaxial layer deposited on the front side, comprising the following process steps:    (a) a removal polishing step as the sole polishing step;    (b) (hydrophilic) cleaning and drying of the silicon wafer;    (c) pretreatment of the front side of the silicon wafer at a temperature of 950 to 1250 degrees Celsius in an epitaxy reactor; and    (d) deposition of an epitaxial layer on the front side of the pretreated silicon wafer.
It is customary, in order to protect silicon wafers from particle loading, to subject the silicon wafers to a hydrophilic cleaning after polishing, in accordance with step (b) in the above process sequence. The hydrophilic cleaning produces a very thin native oxide layer with a thickness of approximately 0.5 to 2 nm, depending on the type of cleaning and measurement. The native oxide is removed during the course of pretreatment in the epitaxy reactor in accordance with (c), usually in a hydrogen atmosphere. This pretreatment step is also known to the person skilled in the art by the term “H2 bake”.
In a second step, likewise provided as a pretreatment step before the actual deposition of the epitaxial layer, the surface roughness of the front side of the silicon wafer is reduced and polishing defects are removed from the surface of the silicon wafer to be epitaxially coated. For this purpose, by way of example, an etching treatment with gaseous hydrogen chloride (HCl) is carried out by adding HCl to the hydrogen atmosphere.
Often, besides HCl, a silane source, for example silane (SiH4), dichlorosilane (SiH2Cl2), trichlorosilane (TCS, SiHCl3) or tetrachlorosilane (SiCl4), preferably trichlorosilane, is also added to the hydrogen atmosphere in an amount such that silicon deposition and silicon etching removal are at equilibrium. Both reactions proceed at a sufficiently high reaction rate, however, so that silicon on the surface is mobile and the surface is smoothed and defects are removed on the surface. The silicon wafer that has been pretreated in this way subsequently acquires an epitaxial layer.
Epitaxy reactors, which are used in particular in the semiconductor industry for the deposition of an epitaxial layer on a silicon wafer, are described in the prior art. During all coating or deposition steps, one or more silicon wafers are heated by means of heating sources, preferably by means of upper and lower heating sources, for example lamps or lamp banks, and subsequently exposed to a gas mixture, comprising a source gas (silanes), a carrier gas (e.g. hydrogen) and, if appropriate, a doping gas (e.g. diborane).
A susceptor, for example one made of graphite, SiC or quartz, serves as a support for the silicon wafer in the deposition chamber of the epitaxy reactor. During deposition of the epitaxial layer, the silicon wafer rests on the susceptor or in milled-out portions of the susceptor in order to ensure uniform heating and to protect the rear side of the silicon wafer, on which generally no layer is deposited, from the source gas.
In accordance with the prior art, the process chambers of epitaxy reactors are designed for one or more silicon wafers. In the case of silicon wafers having relatively large diameters (greater than or equal to 150 mm), single wafer reactors are usually used since the latter are known for good epitaxial layer thickness regularity. The uniformity of the layer thickness can be optimized by various measures, for example by altering the gas flows (H2, SiHCl3), by incorporating and adjusting gas inlet devices (injectors), by changing the deposition temperature, or by alterations to the susceptor.
In epitaxy, it is customary, after one or more epitaxial depositions on silicon wafers, to carry out an etching treatment of the susceptor without a substrate, during the course of which the susceptor and also other parts of the process chamber are freed of silicon deposits. This etch, using hydrogen chloride (HCl), for example, is often already carried out after the processing of a small number of silicon wafers (1-5) in the case of single wafer reactors, and is not carried out until after the processing of a greater number of silicon wafers (10-20) when thin epitaxial layers are deposited.
It has been shown in the prior art that some of the epitaxially coated silicon wafers have a significantly poorer local flatness in the edge region. Thus, by way of example, if an etching treatment of the susceptor is carried out after 4 epitaxial depositions, it may be observed that in each case one of the silicon wafers that are epitaxially coated between two susceptor treatments exhibits a significantly poorer local flatness in the edge region, which in this case has the consequence that 25% of the epitaxially coated silicon wafers do not meet local flatness requirements.
Moreover, the silicon wafers epitaxially coated in accordance with the prior art exhibit an undesirable further decrease in their thickness in the edge region (edge roll-off), which already occurs to some extent in the polished silicon wafers, the silicon wafers usually being polished concavely in order to restrict the edge roll-off to only an outer edge region. A concavely polished silicon wafer is thinner in the center, then increases in its thickness toward the edge and has a decrease in thickness only at the edge.
The edge geometry is usually quantified by specifying one or more edge roll-off parameters which usually relate to the total thickness of a silicon wafer or to the edge geometry of its front and/or rear side, and which can be used to characterize the customarily observed decrease in the thickness of the silicon wafer in its edge region, or the flatness of front and/or rear side of the silicon wafer in its edge region. One method for measuring the edge roll-off of silicon wafers is described in JPN. J. APPL. PHYS., vol. 38 (1999), pp. 38-39.
Edge roll-off parameters relating to the thickness of a silicon wafer can be determined by means of a NanoPro NP1 topography measuring system from KLA Tencor, for example, by firstly calculating 360 radial cross sections with a spacing of 1° of the entire map (topography, “Wafer Map”) of a silicon wafer, starting in the center of the wafer. The cross sections are usually divided into 4 sectors S2 to S5 (90° sectors in each case) and all 90 radial cross sections are averaged for each sector. A matched third order reference line (“best fit”) is calculated for a range of a distance of R-5 mm to R-35 mm from the edge of the wafer. Finally, the fourfold symmetry of the edge roll-off is averaged out (by averaging over all the radial thickness cross sections), and an R30-1 mm parameter is produced, for example, by determining the deviation between the averaged radial cross section and the reference line determined by regression for a distance of R-1 mm from the edge of the wafer. Usually an R30-3 mm parameter for a distance of 3 mm and an R30-2 mm parameter for a distance of 2 mm from the edge of the silicon wafer and possibly intermediate values are determined as well. If the silicon wafer has an edge roll-off, the corresponding R30 parameters have a negative sign.
As an alternative, it is also possible to consider the deviations between average radical cross sections per sector (single traces) and the reference line and thus to obtain a roll-off value for each sector. However, average edge roll-off values are always considered in the context of the present invention.
In the case of silicon wafers which are polished and subsequently epitaxially coated in accordance with the prior art, the R30-1 mm edge roll-off parameter referring to the thickness of the silicon wafer has a magnitude of 100 nm or higher. By way of example, the following values were determined for a silicon wafer epitaxially coated in accordance with the prior art: an R30-3 mm of −42 nm, an R30-2 mm of −105 nm and an R30-1 mm of −304 nm.